To improve the current flowing through the channel of a transistor, the mobility of the carriers in the channel can be increased. This increased mobility of the carriers in the channel typically increases the operational speed of the transistor. It is further known that mechanical stresses within a semiconductor device substrate can modulate device performance by, for example, increasing the mobility of the carriers in the semiconductor device. That is, stresses within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the n-type devices (e.g., NFETs) and/or p-type devices (e.g., PFETs).
However, the same strain component, for example, tensile strain or compressive strain in a certain direction, may improve the device characteristics of one type of device (i.e., n-type device or p-type device) while discriminatively affecting the characteristics of the other type device. Accordingly, in order to maximize the performance of both NFETs and PFETs within integrated circuit (IC) devices, the strain components should be engineered and applied differently for NFETs and PFETs.
Distinctive processes and different combinations of materials are used to selectively create a strain in a FET. For example, liners of different materials on gate sidewalls have been used to selectively induce the appropriate strain in the channels of the FET devices. By providing gate liners the appropriate strain is applied closer to the device. While this method does provide tensile strains to the NFET device and compressive strains along the longitudinal direction of the PFET device, using different materials, they may require additional materials and/or more complex processing, and thus, result in higher cost. Further, the level of strain that can be applied in these situations is typically moderate (i.e., on the order of 100 s of MPa), and it is difficult to optimize the stress levels needed for high performance devices. Thus, it is desired to provide more cost-effective and simplified methods for creating larger tensile and compressive strains in the channels of the NFETs and PFETs, respectively.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.